(1) Field of Invention
The present invention relates to methods used to fabricate semiconductor devices and more specifically to methods used to control the series resistance of lightly doped source and drain, (LDD), regions.
(2) Description of Prior Art
Metal oxide semiconductor field effect transistor, (MOSFET), devices can be fabricated as N channel, or P channel devices. The P channel, or PMOS devices feature P type, LDD regions as well as P type doped, polysilicon gate structures. These P type regions, comprised with boron ions, can however experience decreased boron concentration during thermal cycles encountered during subsequent processing sequences. The affinity of boron for silicon oxide, can result in boron, located in the polysilicon gate structure, or in the LDD region, diffusing from these regions to adjacent silicon oxide regions, such as pad oxides on the LDD region or silicon oxide spacers on the polysilicon gate structures, during subsequent anneal cycles.
The present invention will describe several solutions for reducing the diffusion of boron from both P type polysilicon gate structures, as well as from P type, LDD regions, into adjacent silicon oxide regions, thus reducing the risk of increased LDD resistance, which can result from the unwanted boron diffusion phenomena. Prior art, such as Chao et al, in U.S. Pat. No. 5,629,221, offer a process of implanting nitrogen, through a polysilicon layer, to form a barrier layer to prevent boron out diffusion, at a gate insulator interface. The present invention will offer solutions to the boron diffusion phenomena which however will not involve the gate oxide layer, thus not risk compromising gate oxide integrity.
It is an object of this invention to retard boron out diffusion from a P type polysilicon gate structure, and from P type, LDD regions, via formation of a monolayer of silicon nitride at the interface of the LDD or polysilicon gate-silicon oxide interface, accomplished via a plasma nitridation procedure performed after a polysilicon reoxidation procedure.
It is another object of this invention to retard boron out diffusion from a P type polysilicon gate structure, and from P type, LDD regions, via formation of a silicon oxynitride formed on the surface of the P type, polysilicon gate structure, and on the surface of the P type LDD regions, via introduction of a nitrogen source during the polysilicon reoxidation procedure.
It is yet another object of this invention to retard boron out diffusion from a P type polysilicon gate structure, and from P type, LDD regions, via deposition of a thin silicon nitride layer on the surface of the oxide formed after the polysilicon reoxidation procedure.
In accordance with the present invention methods used to form a nitrogen containing layer, used to retard diffusion of boron from P type polysilicon gate structures, and from P type, LDD regions, into adjacent silicon oxide layers, are described. A first method features a polysilicon reoxidation procedure resulting in the formation of a silicon oxide layer on the surfaces of a P type polysilicon gate structure, and on the surface of P type, LDD regions. An RF plasma treatment is then performed using a nitrogen source, to form a silicon nitride monolayer at the interface of the silicon oxide-polysilicon gate, or LDD region. A second method used to retard boron diffusion from the P type elements is the addition of a nitrogen, to the ambient used for the polysilicon reoxidation procedure, resulting in a silicon oxynitride layer, on the surfaces of the P type polysilicon gate structure and on the surfaces of the P type LDD regions. A third method used to retard boron out diffusion is the chemical vapor deposition of a thin silicon nitride layer on the surface of a polysilicon oxide layer, formed on the exposed surfaces of the P type polysilicon gate structure, and the P type LDD regions. An overlying silicon oxide layer is then formed via chemical vapor deposition procedures, using tetraethylorthosilicate, (TEOS), as a source, followed by the formation of an overlying thick silicon nitride insulator spacer. Heavily doped, P type source/drain regions are then defined via ion implantation procedures, using the thick insulator spacer as a mask.